The invention relates to a method and a device for testing set-up time and hold time of signals of a circuit with clocked data transfer.
In order to ensure completely satisfactory functioning in the course of data transfer, in particular in read/write memories, it is necessary to comply with specific temporal boundary conditions. In particular, it is important in the course of data transfer that a time frame is observed in which the signal to be assessed is constant, in order to be able to be correctly assessed and thus unambiguously identified. This time frame is composed of a set-up time and a hold time, the set-up time denoting that time window which begins at a relative instant before the rising or falling edge of a clock pulse and ends with a defined level of the relevant clock pulse edge. The hold time is to be understood as that time window which begins with a defined level of the rising or falling edge of a clock pulse and ends at a relative instant after the relevant edge.
The volumes of data which are intended to be transmitted in modern data transfer systems, for example in a read/write memory, are becoming greater and greater. The consequence of this is that the transmission cycles are becoming shorter and shorter. Thus, e.g. read/write memories are known which use clock pulses for data transfer at a frequency of 400 MHz, which enables a data transfer rate of 800 MHz since two data transfers are carried out in one clock period, namely both at the rising and at the falling edge of the clock pulse. In order to be able to correctly assess the transmitted signals at such a transmission frequency, a time frame of 400 ps is typically required, in which the transmitted signals must be constant in order to be able to be correctly assessed. In this case, this time frame is preferably divided into two symmetrical time windows around the edge of the clock signal, that is to say into a set-up time and a hold time of 200 ps in each case.
Before a circuit with clocked data transfer is incorporated into a data transfer system, that is to say e.g. a read/write memory into a computer, it is usually necessary to test the circuit and, in the process, to determine in particular the set-up time and the hold time. The very short set-up time and hold time e.g. in very fast read/write memories necessitate a high technical outlay for testing these time windows. In conventional practice, therefore, extremely expensive precision product testers with very high testing accuracy must be used.
International PCT publication WO 00/13186 discloses a system and a method for testing read/write memories in which a test module is integrated on the chip with a fast read/write memory in order to generate the time-critical signals for testing the set-up time and the hold time. In this case, an oscillator connected to the test module is used to apply a time signal to a clock generator of the test module, which generates the clock signals for the data transfer of the read/write memory. These clock signals are applied in parallel to the read/write memory to be tested and to a monitoring unit, a delay unit being provided which makes it possible to shift the clock signal relative to a fixedly predetermined write or read signal in order thus to define the time window in which data must remain constant in the course of data transfer in order to be correctly assessed. In this case, the delay unit is programmable in order to be able to set both the set-up time and the hold time.
One problem with the prior art test module, however, is the exact programming of the delay unit in order to preclude testing inaccuracies. Thus, an extremely fine gradation of the setting range of the variable delay time relative to the period of the clock pulse is necessary in order to be able to accurately determine the set-up time and the hold time. This requires a high degree of accuracy in the setting of the delay, and hence increased costs.
The object of the present invention is to provide a method and a device for testing the setup time and the hold time of signals in a circuit with clocked data transfer which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which is distinguished by a simple construction and high testing precision.
With the above and other objects in view there is provided, in accordance with the invention, a method of testing set-up time and hold time of signals of a circuit with clocked data transfer, which comprises the following method steps:
for testing, applying a reference clock signal with a given period to a first delay path having a fixed delay and to a second delay path having a variable delay, wherein the first delay path is connected to a first input of a clocked circuit for applying a clock signal, and the second delay path is connected to a second input of the clocked circuit for applying a data signal, the variable delay having a setting range xcex94tv with n equidistant steps and a basic delay xcex94t in a range from (tFxe2x88x92nxcex94t/2) to (tF+nxcex94t/2), where tF is a fixed delay and tF is at least nxcex94t/2; and
for calibrating, increasing the given period of the reference clock signal, and the setting range xcex94tv of the variable delay and the fixed delay tF each to a k-fold value and incrementing the variable delay in steps from n=0 until three phase cycle completions are detected, wherein a value of n at an instant of the first phase cycle completion corresponds to the variable delay for the set-up time and the value n at an instant of the third phase cycle completion corresponds to the variable delay for the hold time.
In other words, for testing purposes, a reference clock signal is applied to a first delay path having a fixed delay and a second delay path having a variable delay, which are each connected to an input of the clocked circuit in order to initiate data transfer of the clocked circuit, the first delay path applying a clock signal and the second delay path a data signal to the clocked circuit, the variable delay having a setting range xcex94tv with n equidistant steps and a basic delay xcex94t in the range of [tFxe2x88x92nxcex94t/2; tF+nxcex94t/2] and the fixed delay tF being at least nxcex94t/2. For calibration, the period of the reference clock signal, the setting range of the variable delay and the fixed delay are in each case increased to the k-fold value and the variable delay is incremented in a stepwise manner from n=0 until three phase changes are detected, the value of n at the instant of the first phase cycle completion corresponding to the variable delay for the set-up time and the value of n at the instant of the third phase cycle completion corresponding to the variable delay for the hold time.
This calibration technique enables the set-up time and the hold time to be defined very simply and accurately even in the case of extremely short time windows, since increased precision in the course of setting is achieved by virtue of the multiplication of the delay in the form of a delay magnification during the calibration.
In accordance with an added feature of the invention, a further calibration measurement is carried out and the variable delay is thereby incremented in steps from n=0 until a phase cycle completion occurs, where a difference between the value in the case of this phase cycle completion and the value in the case of the second phase cycle completion of the first calibration measurement corresponds to the propagation time difference between the signals on the fixed delay path and the variable delay path.
With the above and other objects in view there is also provided, in accordance with the invention, a device for testing set-up time and hold time of signals of a circuit with clocked data transfer, comprising:
a first terminal for applying a reference signal with a given period, a second output connected to a first input of a clocked circuit, and a third output connected to a second input of the clocked circuit;
a first delay path connected to the second output, the first delay path having a fixed delay tF;
a second delay path connected to the third output, the second delay path having a variable delay with a setting range xcex94tv with n equidistant steps and a basic delay xcex94t in a range from (tFxe2x88x92nxcex94t/2) to (tF+nxcex94t/2), and wherein the fixed delay tF of the first delay path is at least nxcex94t/2;
a calibration unit connected for calibrating the first delay path and the second delay path, and wherein, for calibration, the period of the reference clock signal, the setting range xcex94tv of the variable delay, and the fixed delay tF are each increased to a k-fold value and the variable delay is incremented in steps from n=0 until three phase cycle completions are detected, and wherein a value of n at an instant of a first phase cycle completion corresponds to the variable delay for the set-up time and the value of n from the instant of the third phase cycle completion corresponds to the variable delay for the hold time.
In accordance with an additional feature of the invention, the calibration unit is configured for carrying out a further calibration measurement in the course of which the variable delay is incremented in steps from n=0 until a phase cycle completion occurs and a difference between the value of n upon the phase cycle completion and the value of n in the case of a second phase cycle completion of a first calibration measurement is determined as propagation time difference between the fixed delay path and the variable delay path.
In accordance with another feature of the invention, the circuit is commonly integrated with the circuit (or circuits) to be tested on a common chip.
In accordance with a further feature of the invention, an input circuit is connected to the first terminal, the input circuit buffering an applied periodic reference signal for generating therefrom a test signal.
In accordance with again a further feature of the invention, each of the first delay path and the second delay path include a respective amplifier unit.
In accordance with a concomitant feature of the invention, an inverting device is connected to one of the first delay path and the second delay path for inverting a respective output signal.
In accordance with a preferred embodiment of the invention, the calibration can furthermore be effected by the test circuit itself, thereby significantly reducing the calibration outlay.
In accordance with a further preferred embodiment, in a second calibration cycle, the variable delay is incremented in a stepwise manner from n=0, the variable delay and the fixed delay not being increased to the k-fold value, with the result that only one phase cycle completion occurs. The difference between the value of n or the associated variable delay in the case of this phase cycle completion and the value of n or the associated variable delay in the case of the second phase cycle completion of the first calibration cycle corresponds to the propagation time difference between the two signal paths, i.e. the fixed delay path and the variable delay path. By taking account of this propagation time difference between the two signal paths, it is possible to achieve an increased precision in the course of setting the set-up time and the hold time.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and device for testing set-up time and hold time of signals of a circuit with clocked data transfer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.